The present invention is an improvement of prior art methods for verifying IC process simulations.
The manufacture of integrated circuits is a complicated and expensive process sometimes involving dozens of process steps. To ensure that this manufacturing effort is not wasted, steps of the IC fabrication process are often modelled in process simulators to determine beforehand whether resulting device features will have the desired width, thickness, cross-sectional profile, etc.
One of the critical steps in IC manufacturing is photolithography, which is used to define key features of an integrated circuit, including active regions, transistor gates, and signal and interconnect lines. In photolithography, a photosensitive polymer photoresist is deposited on a silicon substrate, exposed by a patterned light, then chemically developed. Depending on the type of photoresist, during developing the exposed photoresist is removed (positive photoresist) or retained in preference to the unexposed photoresist (negative photoresist), which results in the formation of a patterned photoresist. Using the patterned photoresist as a mask, further IC processing steps can then occur, possibly including etching and ion implantation, oxide growth or metallization for signal lines or interconnects.
Ideally, IC features created by photolithography would have straight, vertical sidewalls. However, in reality, the sidewalls of a photolithographically defined IC feature can deviate substantially from straight and vertical, which can cause problems in subsequent IC processing steps. FIG. 1, which is a cross sectional view of a resist feature (the shaded region represents unexposed positive photoresist remaining after developing) formed by photolithography, shows two possible sidewall deviations. The first, sidewall scalloping 102, is caused by standing waves set up in the photoresist due to interference of the light used to expose the photoresist. Assuming a positive resist, when the exposed photoresist is subsequently developed, sidewall areas of the photoresist which were underexposed (i.e., in an interference intensity minimum) will not be removed; areas that were overexposed (i.e., in an intensity maximum) will be removed. As a result, the sidewalls of the remaining photoresist in FIG. 1 show a scalloped pattern with trough to peak variations that could be as much as 25% of the width of the areas between the sidewalls. Accordingly, this scalloping can dramatically affect the size of features, especially linewidths, resulting from the subsequent processing steps (e.g., a signal line might be 25% wider or narrower than desired).
The second, a non-vertical sidewall angle/slope 104, is primarily a function of resist contrast, numerical aperture and partial coherence. As FIG. 1 shows, a typical sidewall angle 104 results in a trench in a 1.3 .mu.m-thick resist that has a cross-sectional width that varies from approximately 0.5 .mu.m at the top of the trench to approximately 0.6 .mu.m at the bottom of the trench. Thus, as with scalloping, a pronounced sidewall angle could significantly alter the dimensions of features defined through photolithography. Consequently, it is extremely important that these sidewall characteristics are accurately modelled by process simulators.
Existing process simulators, such as PROLITH/2.TM. and SAMPLE.TM. model sidewall scalloping and angle and other effects of a particular photolithographic process. Results from these simulators are typically verified through scanning electron microscope (SEM) examination of a cross section and feature widths of a photolithographically defined surface. However, while SEM verification is adequate for relatively large-scale features (i.e., a few microns and up), SEMs are generally not able to capture critically important cross-sectional details, such as sidewall scalloping and angle, of features defined by submicron photolithography.
This is because SEMs charge the resist sample under examination with electrons, which has the effect of blurring surface edges on photographs taken of the imaged surface. While blurring is not a significant problem for surfaces with macroscopic features, it tends to obliterate submicron details such as sidewall angle and scalloping. Another problem with SEM metrology is that, typically, IC feature sizes are determined by direct measurement of the SEM photographs with a precision ruler. Besides the obvious problem of making measurements from the blurred edges described above, direct measurement can result in additional errors due to (1) incorrect placement of the ruler on the edge of a photographed feature (assuming the feature edge is identifiable) and (2) the difficulty of measuring the pitch or angle of a cross-sectional feature with a ruler. In the case of submicron devices, these errors can amount to a significant percentage of the feature being imaged. Additionally, SEMs can physically alter the device features being measured.
Other aspects of process models in need of verification include basic process variables such as the developing rate associated with a particular developing solution. By developing a semiconductor wafer in stages and measuring the change in surface profile after each stage, developing rates can be better quantified, resulting in a more accurate process model. However, given the above mentioned measurement errors associated SEM surface imaging, it is not possible to accurately quantify such process variables using SEM metrology.
Moreover, given the inherent lack of reliability (i.e., reproducability of measurements) of SEM metrology as applied to submicron features, it is not possible to use SEM measurements to iteratively adjust the process simulator to model better the results of a particular IC manufacturing process. That is, the SEM is better suited to rough verification of a model rather than incremental improvement of a model.
Finally, given the current lack of a reliable method for verifying and updating process models with respect to submicron IC device features, it is not currently possible to modify IC manufacturing/processing steps in accordance with the predictions of an improved process simulator.
Consequently, there is a need for an IC process model verification system that incorporates a measuring device that can accurately measure the cross sections of submicron device features. There is also a need for an IC process model verification system that can update the IC process model based on those accurate cross-sectional measurements. Finally, there is a need for an IC process model verification system that generates an updated set of IC processing steps reflecting the updated IC process model.